Background & Objectives

Advanced earth bound communication and survey satellites enable new business models but demand also deeply integrated electronics aboard the satellites, either for digital and analog functions. Miniaturized equipment allows for drastic reductions of the satellite mass, thus enabling larger payloads and more service revenues, and lighter satellites resulting in cheaper launches.

However, efficient and competitive packaging of large components remains a roadblock in trying to further downsize the electronic equipment. This is especially true for IC-dies with an area beyond 300 mm² and/or more than 625 pins. Moreover the increased power dissipation of such chips with up to 10 or 20 W is challenging.

Following-up on innovative technologies previously developed by the consortium members in the field of System In Package (SIP) technologies and High Density PCB the major objective of the project is to design, build-up and ECSS qualify a “macro-component” demonstration model (DM) for SiP in space applications, addressing the following challenges:

• High interconnection density,
• Large die dimensions,
• High wiring and component density,
• Overall cost reduction by a factor of 3 compared to ceramic build-up

The project is set up in 3-phases, leveraging advanced technologies in

• organic high density low CTE PCBs,
• innovative thermal management and
• SIP integration

up to TRL7, validating the full industrial processes vs. the ECSS Q ST standards. Furthermore a robust European supply chain serving additional markets beyond space equipment, such as embedded macrocomponents for automotive, defense or aeronautics.

Download

Presentation (Apex Expo IPC 2023)

High density PCB technology for high reliability applications using Low CTE material (.pdf/ 650KB)

Abstract
The space- and other high reliability markets are continuously driven towards an increased use of deeply integrated electronics. The increasing demand for complexity and functionality results in the use of large package components with a high number of I/Os. In order to allow the use of components with high pin counts up to 1752, complex high-density interconnect (HDI) printed circuit board (PCB) technology is required. Reconciling the use of multiple laser-drilled microvia levels in a stacked configuration with the reliability requirements for space is challenging when using heritage dielectric materials. The use of ceramic filled low CTE material allows the manufacturing of complex HDI PCB technology with a high reliability.

The work presented in this paper is part of an ongoing European (Horizon 2020) “COMAP-4S” project on components and macro components packaging for space. The Project is coordinated by SAFRAN ELECTRONICS AND DEFENSE with partners ACB, TUB and NANOXPLORE. The most complex PCB technology targeted within the project is four levels of microvias, requiring the use of low CTE laminate material. The reliability of different microvia configurations from all four levels staggered to all stacked was evaluated using test methods as described in ESA’s ECSS-Q-ST-70-60C standard for qualification and procurement of printed circuit boards. The test results of various material-level reliability tests, interconnection stress testing (IST) and reflow simulation combined with rework and traditional thermal cycling are provided to demonstrate a high reliability of the different via configurations and overall PCB technology.

Download full paper here (.pdf/2MB).